The field of the present invention pertains to the field of integrated circuit design optimization using electronic design automation tools. More particularly, aspects of the present invention pertain to a power dissipation optimization process for use in the design of complex integrated circuits with electronic design automation (EDA) tools.
Computer systems, software applications, and the devices and processes built around them are continually growing in power and complexity. Society""s reliance on such systems is likewise increasing, making it critical that the systems deliver the expected performance and obey the properties that their designers intended. As each successive generation of computer and software implemented systems and processes become more powerful, the task of designing and fabricating them becomes increasingly difficult.
Increasing levels of integration allow much higher circuit densities per integrated circuit die. Higher circuit densities allow higher operating speeds. During the operation cycle of a high-density integrated circuit, a certain amount of power will be drawn by the integrated circuit. This amount of power depends upon the types of operations the circuit is performing. For example, operations requiring large amounts of switching produce correspondingly large amounts of power dissipation.
Hence, the power dissipation experienced by the integrated circuit varies over time as the integrated circuit functions. During certain operations, the integrated circuit will experience peak power dissipation, where the amount of power dissipated by the circuit per unit of time is at maximum. Peak power affects the amount of heat generated by the integrated circuit. Peak power typically equates to peak heat generation, and thus, peak power characteristics are among the most important design constraints for new integrated circuit devices.
The design and manufacture of increasingly complex integrated circuits involves extensive use of CAD tools. The development of ASICs (application specific integrated circuits) and other complex integrated circuits using CAD tools is referred to as electronic design automation, or EDA. The design, checking, and testing of large-scale integrated circuits are so complex that the extensive use of CAD and EDA tools are required for realization of modern, complex integrated circuits.
The development of a new integrated circuit device begins with a design phase involving extensive use of EDA tools to facilitate various aspects of designing the new integrated circuit device. Typically, EDA tools function in part by decomposing the overall desired behavior of the integrated circuit into simpler functions which are more easily manipulated and processed. The EDA tool performs considerable computation to generate an efficient layout of a resulting xe2x80x9cnetworkxe2x80x9d of design elements (e.g., logic gates, storage elements, etc.). The resulting network, commonly referred to as a netlist, comprises a detailed specification defining the integrated circuit, typically in terms of a particular fabrication technology (e.g., CMOS). The netlist can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
Netlists for integrated circuit designs can represent a particular integrated circuit in different levels of abstraction, such as the register transfer level (RTL) and the logical level, using a hardware description language (HDL), also called high level design language. The HDL description is used along with a set of circuit constraints as an input to a computer-implemented compiler (also called a xe2x80x9csilicon compilerxe2x80x9d or xe2x80x9cdesign compilerxe2x80x9d). The compiler program processes the HDL description of the integrated circuit and generates therefrom a low-level netlist comprised of detailed lists of logic components and the interconnections between these components. The components specified by the netlist can include primitive cells such as full-adders, NAND gates, NOR gates, XOR gates, latches, and D-flip flops, etc., and their interconnections. In recent years the design process has become increasingly powerful and sophisticated, yielding very large, very complex high density integrated circuit devices.
Increasing levels of integration allow much higher circuit densities per integrated circuit die. Higher circuit densities allow higher operating speeds. During the operation cycle of a high-density integrated circuit, a certain amount of power will be drawn by the integrated circuit. This amount of power depends upon the types of operations the circuit is performing. For example, operations requiring large amounts of switching produce correspondingly large amounts of power dissipation.
Hence, the power dissipation experienced by the integrated circuit varies over time as the integrated circuit functions. During certain operations, the integrated circuit will experience peak power dissipation, where the amount of power dissipated by the circuit per unit of time is at maximum. Peak power affects the amount of heat generated by the integrated circuit. Hence, peak power typically equates to peak heat generation.
Heat generation is not uniformly spread across the area of the integrated circuit. Peak heat generation corresponds to peak power requirements, which in turn corresponds to circuit switching activity. For example, during certain operations some portions of the integrated circuit may be relatively inactive (e.g., memory elements) while other portions are highly active (e.g., arithmetic logic units). The non-uniform heat generation leads to the development of xe2x80x9chot spotsxe2x80x9d within the area of the integrated circuit die. The hot spots are the first areas of the integrated circuit to be adversely affected by higher levels of heat generation.
Thus, the existence and the characteristics of such hot spots are one of the primary limiting factors on the maximum potential operating speed of the integrated circuit. Accordingly, xe2x80x9cpeak powerxe2x80x9d is an important parameter that affects the life of circuit. Excessive localized heat generation leads to thermal breakdown of the actual integrated circuit elements themselves (e.g., electron migration, etc.).
In accordance with the prior art, circuit developers use EDA tools (e.g., netlist simulations, etc.) during the design phase in an attempt to predict the peak power dissipation of the device, and thereby design higher performance integrated circuit devices. For example, a netlist description of the device is loaded onto an EDA simulation tool for optimization in accordance with, for example, a set of power dissipation constraints. The simulation tool stimulates the netlist using a large series of test inputs in an attempt to stimulate its operation and predict therefrom the power requirements and characteristics of the device. The results of the simulation allow the device to be optimized with respect to peak power and peak heat generation. Increasing levels of integration unfortunately leads to increasing complexity of the simulation and a corresponding increase in the difficulty of the optimization process.
As described above, peak power in high-density integrated circuits has a great impact on power budgeting, packaging, as well as circuit""s reliability. However, performance and reliability requirements continue to drive the design process towards ever greater levels of integration and ever greater operating speeds. To synthesize highly reliable systems, accurate estimates of maximum power must be obtained in various design phases. Unfortunately, determining the input patterns (e.g., inputs to the netlist of integrated circuit) to induce the maximum current (power) is essentially a combinatorial optimization problem. Even for circuits with small number of primary inputs, it is computer time intensive to conduct exhaustive search of the input vector space.
Because of this large input vector space, the compiling and optimization of large integrated circuit designs typically require one, or more, of the most powerful CAD workstations. Large amounts of memory are required to store the details regarding the various aspects of the netlist and large amounts of CPU time are required to perform the various compilation and optimization routines on the netlist. For example, successive passes through the design phase (e.g., in an attempt to rectify abnormally intense hot spots) is often required in order to optimize a design completely with respect to peak power constraints, and can be very impractical. Thus, circuit designers often resort to merely finding good upper and lower bounds of the peak power, and to make the gap between these two bounds as narrow as possible, within a reasonable amount of time. Because of this, large designs are typically not optimized is vigorously as smaller designs.
This lack of thoroughness in power optimization leads to a number of serious consequences. For example, non-optimal power dissipation leads to fabricated integrated circuit devices which are less than optimally efficient (e.g., shorter circuit life, larger than necessary die size, slower performance, greater power consumption, and the like).
Accordingly, what is required is a system capable of efficiently optimizing large complex integrated circuit designs for power dissipation. What is required is a system capable of vigorously optimizing a complex integrated circuit design for power dissipation within the reasonable time and resource constraints of modern EDA design synthesis processes. The present invention provides a novel solution to these requirements.
The present invention provides a system capable of efficiently optimizing large complex integrated circuit designs for power dissipation. The present invention provides a method and system capable of vigorously optimizing a complex integrated circuit design for power dissipation within the reasonable time and resource constraints of modern EDA design synthesis processes.
In one embodiment, the present invention is implemented as a genetic algorithm (GA) based process to optimize integrated circuit designs for power dissipation. The genetic algorithm optimization process efficiently generates tight lower bounds of the peak power dissipation for a given integrated circuit design. In this approach, the power within a given integrated circuit design is viewed as a function in terms of a set of stimuli to primary inputs of the integrated circuit design. Maximization of the function, and hence, the power dissipation, is guided by the genetic algorithm. By repeatedly stimulating the integrated circuit design and measuring the corresponding response, the genetic algorithm process of the present invention efficiently explores the solution space to obtain a maximization of the function.
The genetic algorithm process is implemented within a computer-based EDA synthesis system. The EDA synthesis system executes the computer implemented steps of accessing a circuit netlist representing an integrated circuit design to be realized in physical form, defining a function that describes the power with respect to stimulation, maximizing the function by using a genetic algorithm to obtain a set of stimulation inputs which generate a maximum power dissipation, and optimizing power dissipation for the circuit netlist by optimizing those portions of the circuit netlist identified by the set of stimulation inputs.
By repeatedly stimulating the circuit and measuring the corresponding response, GA efficiently explores the solution space through mechanisms analogous to natural selection. These mechanisms include, for example, GA operations such as crossover, mutation, reproduction, and the like. Targeting large-scaled, high density designs in deep sub-micron technology, the EDA synthesis system of the present invention drives the GA xe2x80x9cevolutionxe2x80x9d process of power optimization. For example, experiments with ISCAS-85 and ISCAS-89 benchmarks demonstrate the superiority of the optimization process of the present invention. Compared with the conventional prior art random simulation based techniques, the GA-based power dissipation optimization process can generate tighter lower bounds within shorter time. In so doing, the GA based optimization process of present invention is capable of vigorously optimizing a complex integrated circuit design for power dissipation within the reasonable time and resource constraints of modern computer implemented EDA design synthesis processes.